Scripting skills: Tcl, boundary scan , Vcs, System Verilog, Memory BIST, primetime, Logic Equivalency checking, Post-silicon validation and debug, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, EDA Tools, BIST architectures, Tessent tool sets, TestMax

boundary scan , Vcs, Perl, Python, System Verilog, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax

boundary scan , Vcs, Perl, System Verilog, Python, Tcl, primetime, Logic Equivalency checking, Jtag protocols, memory BIST, TetraMax, Gate level simulation debugging, Scan and BIST architectures, ATPG, EDA Tools, Tessent tool sets, TestMax

boundary scan , Vcs, Perl, Python, System Verilog, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax