simvision , Verilog simulations, Digital Mixed Signal Verification, UVM Test Bench, SystemVerilog PLI coding, Hspice, Verilog Real Number Models, vsim, Xcellium, Finseim, virtuoso, Waveview, SV UVM based Verification, systemverilog

C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Debug features, UPF support, systemverilog, Scan Boundary Scan, VHDL, DFX Design Planning, Low Power technologies

commissioning support , Testing, Validation, Sat, Interlocks, Plc, Permissives, Alarms, Virtual controllers, Model-based validation environments, Trip logic, Simulation Tools, Control logic design, Turbine control platforms, Gas Turbine Controls, Dcs, GE Mark VIe, PID loops, FAT, sequencing, Protection logic, swat

C, Verilog, System Verilog, Python, interrupt-engines, no-OS test frameworks, CPU boot-devices, MMU, DMA, Device-Driver concepts, IOMMU, SOC and System Architecture

Servicenow, Automation Frameworks, Automated test scripts, Testing Methodologies, Continuous Deployment, Continuous Integration

Windows Server, Linux, Automation Frameworks, Networking Protocols, PowerShell, Rhel, TLS Protect, Venafi TPP, PKI engineering, API integrations, certificate lifecycle management

Selenium, Test Automation Tools, Automation Frameworks, Guidewire applications, Playwright

Sdet, Api Testing, Microservices, Test Engineering, Typescript, Qa Automation, Automation Frameworks, AWS, REST-based testing frameworks, cloud-native systems, Playwright, event-driven architectures, CI CD, configuration-driven systems, GitHub Actions, Cypress, feature flags, E2E frameworks, debugging skills