code coverage , System Verilog, IC verification tools, Cover groups, DIMM, DDR5, DDR4, Uvm, Functional coverage, Assertions, LPDDR5

Pvs, Perl, Python, Tcl, pegasus, LVS, Voltus, DRC, QRC, EM and thermal analysis platforms, Quantus, Thermal analysis concepts and extraction methodologies, Automated engineering workflows

Perl, Python, ASICs, Analog behavioral models, System Verilog Programming, Chipsets, Digital Verification

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

Autocad, Catia V5, Wiring harness design, regular expressions, ATIM, VeSyS2.0 wiring harness design tool, Wiring harness testing and inspection, Basic Python scripting, IPC-620 standard, CAD Tools, MENTOR TOOLS

Debugging, Soc Architecture, Perl, Verilog, Python, Tcl, Sta, High-speed digital design, cdc, Low-power design concepts, IP integration, systemverilog, FPGA prototyping, Rtl Design, Synthesis, Micro-architecture