Automation SKILL coding, Full chip layout experience, Analog and mixed-signal layout techniques, Device Matching, Power Bus design, ESD LU protection techniques, LVS DRC ERC and antenna debug skills

Synopsys IC Validator, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, Cadence Pegasus, high-speed analog and mixed-signal layout design, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, DRC, parasitic optimization, reliability rules

Analog layout techniques, Device matching EM IR, Calibre DRC LVS

layout verification , automation, Cadence VLE, Mentor Graphic Calibre DRC, Layout Design, AI tools, skill coding