Analog circuit architectures, Analog layout concepts, Analog Mixed-Signal IC Design, Post-layout simulations, CMOS technology, Spectre ADE, Design-to-silicon cycle, Cadence Virtuoso

System Integration, Matlab, Signal Grounding, Monte Carlo Analysis, Physical Layout Management, Top-level Verification, Block-level Modeling, AMs, Post-layout Parasitic Extraction, Architectural Tradeoff Analysis, Block-level Topology Selection, IC System Partitioning, Spectre, Worst-case Identification, Schematic Generation, Simplis, Routing Tradeoffs, Device Physics Knowledge

circuit testing , clocking circuits, analog to digital converters, CMOS technologies, Circuit Simulation, LDO, analog power circuits, analog fundamentals, Analog Electronics, analog behavior modeling

UNIX, signals systems and transforms, MOS transistors, Analog Circuit Design, layout tradeoffs, layout verification tools, device physics, High Volume Manufacturing, feedback systems, Mixed Signal Design, AC DC analysis, circuit simulation tools, CMOS Bi-CMOS fabrication processes, poles zeros compensation, loop dynamics, Modeling Tools, end-to-end design flow

Cadence Virtuoso, analog and mixed-signal circuit design, high-speed analog architectures, Signal Integrity, jitter, Spectre, advanced CMOS technology nodes

temperature sensors , bandgap references , AC simulations, Spectre AMS, mixed-signal circuit design, DNL, ADEXL, op-amps, biasing circuits, INL, Cadence Virtuoso suite, low-noise Sigma-Delta converters, Layout XL, THD, precision analog circuits, CMOS technologies, DC operating point, noise, Schematic Maestro, Stability, frequency response, LDOs, mismatch analysis

Low-Noise Amplifier (LNA) design, Debugging, Cadence Tools, Monte Carlo analysis, floorplanning, Noise optimization techniques, Flicker noise reduction, Spectre, Thermal noise budget management, Calibre, Shield strategy, High-precision test equipment, SAR ADCs, Analog layout matching, characterization, Ultra-low-power analog circuit design, virtuoso, Column-parallel ADC architectures, Deep sub-micron CMOS process nodes, Parasitic Extraction, Silicon bring-up

Schematic Design, References, Simulation, Protection Circuits, Data Converters, power management, Analog Layout Effects, ESD Latch-Up, Control-Loop Stability, Mixed-Signal IC Development, Switching Converters, Sensors, Analog Feedback Loops, Signal-Conditioning Blocks, IC-Level Robustness, LDOs, Charge Pumps, Analog Design, Post-Layout Verification