Company Description

SiSoC Semiconductor Technologies Pvt. Ltd. is a leading IP and Design services company specializing in Digital, Analog, and Mixed Signal design and verification. With expertise spanning ASIC/SoC Design Verification, Physical Design, DFT, FPGA Emulation, Embedded Software, and IoT solutions, we deliver high-quality and reliable engineering services. Our skilled team leverages advanced tools, technologies, and methodologies to provide end-to-end design and verification solutions, including specification definition, RTL coding, synthesis, and verification environment development. At SiSoC, our specialty is integrating modern design practices with cutting-edge innovation to meet the unique needs of each project.

Role Description

This is a full-time remote role for a Lead/Manager/Director Design Verification Engineer. The selected candidate will lead and manage design verification tasks, including verifying ASIC/SoC designs, developing and executing verification strategies, and creating and maintaining test benches. Day-to-day responsibilities include collaborating with cross-functional teams, defining and implementing advanced verification methodologies, performing debugging, and ensuring adherence to quality standards and timelines.

Responsibilities & Competencies

Exp: 8+ Years

Location: Bangalore

What you will do

We are looking for someone to strengthen the ASIC Top level team with respect to GLS.

We are currently developing two main dies to be instantiated in various configurations in different ASICs.

One die consists of a huge number of DSPs and even more accelerator IPs for different type of computing. The same die also a common memory used by all DSPs and accelerators IPs.

Role in the Team

When working with GLS you will be involved in

Tailor the SystemVerilog/UVM testbench to support GLS
Verify power-up and reset sequence
System initialization
Verify all interfaces that are used for the silicon bring-up

Skills you bring

Skills you must possess:

Experience of GLS of large ASIC designs, zero delay as well as with annotated SDF.
Experience X-propagation debug.
Solid RTL and netlist debugging skills in SystemVerilog or VHDL designs.
C-programming experience, to be able to modify tests if necessary
Understanding of how to reduce long simulation time of very large ASIC designs. This e.g. requires an understanding of how to user grey box/black box concept from IP level to chiplet level.
Understand what to initialize and when, to get the GLS working.
Experienced with Verdi on large designs.

Other desired knowledge and experience:

Experience with git, Gerrit and Jenkins.
Some experiences from external interfaces is a plus

Lead/Manager / Director GLS Verification Engineer