Routing, Perl, Python, Tcl, CTS Clock Optimization, floorplanning, Placement Optimization, IR EM, Synopsys Fusion Compiler, Cadence Innovus, Physical Signoff, Power Planning, Eco, MMMC, PPA Optimization, STA Timing Closure, VLSI Physical Design, Synopsys ICC2

automation, Python, Tcl, place-and-route, Cadence Innovus, Timing Analysis, Physical Verification

Scripting, EDA Tool Proficiency, Cross-Functional Collaboration, Risk Issue Management, Team Leadership Mentorship, SerDes IP Integration, Architecture Methodology, Technical Ownership Project Planning, RTL-to-GDSII Execution, Advanced Technology Nodes, Stakeholder Vendor Alignment, Timing PPA Closure, SoC-Level Physical Design

Tcl Scripting, Shell scripting, Python, Routing, Perl, Sta, Signoff, CTS, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, LVS, Signal Integrity, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2