protocol stack , PCIe Gen4, HBM integration, Root complex endpoint switch architectures, UCIe architecture, LTSSM, Protocol compliance testing, SerDes architecture, Chiplet ecosystem, CXL protocol knowledge, Architecture and verification, System-level performance modeling

C, Pcie, C++, Verification, ARM bus protocols, CHI protocols, CXL

C, System Verilog, Python, Embedded uC Designs, Synthesis, Behavioral coding, Synthesis and SDC Creation, low power design, Digital architecture, Debugging verification test cases, Design Architecture, Design implementation, Synthesis constraint generation, Digital RTL, Low-power designs, Scripting of design automation, AI assisted design practices, power management, Timing Analysis, Dft, uC Based subsystems