Design Analysis, API 6FA, ASME 31.3, Solid Mechanics, Asme, API 6A, NACE MR 0175, FEA structural analysis, Heat Transfer, Fluid Dynamics, API 5CT

simvision , Python, Perl, Tcl, Standard Cell design, Finefet planner, Liberate, ICC2, Solido Analytics, AI-assisted tools, FINESIM, HSIM, lib release, DTCO development, layout and verification, VerilogHDL, block level timing analysis, Siliconsmart, CMOS device physics, CMOS Circuit Design, Skill, primetime, Hspice, RTL GDS flow setup, Cadence Virtuoso

Ovm, Debugging, Unix Shell Scripting, Verilog, System Verilog, Perl, Pcie, Tcl Scripting, DDR, Circuit Analysis, Uvm, IC chip design development flow process, CAE CAD tools, Circuit Design, test bench development, VHDL, AHB, Axi, CMOS logic design, CMOS device operation and characteristics, coverage assertion driven verification, verification plans, Simulation

power optimization , C, C++, Ethernet Switching, Uart, Spi, Verilog, Python, Tcl, Digital design methodologies, Area optimization, systemverilog, Pre-silicon system validation, Timing Closure, TSN, Synthesis, Packet processing, FPGA emulation, I²C, Simulation, Microcontroller-based subsystems, Timing Analysis