deciphering circuit behavior from schematics, DC analysis, netlist simulation, debugging gate level simulation failures, debug failures and provide fixes at gate or transistor level, latch based designs, timing requirements, circuit simulation with spice simulators, spice correlation, path delay simulations, gate level simulation, transient analysis, timing arcs, circuit characterization timing libraries, Verilog MOS switch level models

regulators , references, power-distribution functions, ADCs, noise matching, Filters, mixed-signal design, variability, Spectre, DACs, Feedback, Amplifiers, circuit trade-offs, Analog Design, Cadence Virtuoso, line interfaces, clock-generation circuits, CMOS device behaviour

Silicon Validation, layout techniques, Analog Design, automotive Ethernet, mixed-signal design, IC tape-out, Cadence Virtuoso, Circuit Design, Spectre

Analog Circuit Design, Schematic entry, Post-layout simulations, Lab characterization, Area trade-offs, High-reliability design techniques, Silicon bring-up, Monte-Carlo simulations

advanced semiconductor process nodes, serdes analog design, Microarchitecture, industry-standard tools for circuit design and simulation, Analog Circuit Design