synopsys primetime , Tcl Scripting, Perl, Python, Design Compiler, STA constraints development, RTL to GDSII design flow, Fusion Compiler, SoC timing architecture, Cadence Genus, Cadence Tempus

Shell, Python, Tcl, Signal integrity crosstalk, primetime, Process technologies 7nm 14nm 28nm, Fusion Compiler, Tempus, Cadence Innovus, Static Timing Analysis STA, Floorplanning Placement, Voltus, Mentor Graphics tools Calibre DRC LVS, CTS Routing, Power analysis IR EM, ASIC SoC design flow, Synopsys ICC2

Perl, Python, Tcl, Sta, Mentor Calibre, primetime, Fusion Compiler, Cadence Innovus, Tempus, EDA Tools, Genus, Synopsys ICC2

hardware engineering , Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation