ML optimization tools (DSO.ai), CTS and routing, Timing-driven placement, PPA Optimization, floorplanning, Hierarchical physical design, RTL-to-GDS implementation flow, Synopsys Fusion Compiler, Pin assignment, Timing budgeting

Scripting, EDA Tool Proficiency, Cross-Functional Collaboration, Risk Issue Management, Team Leadership Mentorship, SerDes IP Integration, Architecture Methodology, Technical Ownership Project Planning, RTL-to-GDSII Execution, Advanced Technology Nodes, Stakeholder Vendor Alignment, Timing PPA Closure, SoC-Level Physical Design

Tcl Scripting, Perl, Python, floorplanning, STA timing analysis, PVT analysis, IR EM-related issues, timing ECOs, Cadence Innovus, signoff, Signal Integrity, congestion, CTS routing optimization, full-chip physical design, Timing Closure, setup hold violations, Placement, MMMC SDC constraints, PPA optimization

Netlist2GDS, ASIC design flows, Floorplan, physical design methodologies, power gating, sign-off optimizations, deep sub-micron technology, multi-voltage domains, Circuit Design, device physics

synopsys tools , Tcl Scripting, Asic Physical Design, place-and-route, IC Compiler, Timing Closure, Design Compiler, Fusion Compiler, sign-off, Power Planning, floorplanning

redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus

PERL, Python, Tcl, Synthesis, Formal Equivalence, DRC, Ir, LVS, EM Signoff