Verplex LEC, spyglass, Verilog RTL coding, high-performance memory subsystems, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, ASIC debugging

high-performance datapath architecture, ASIC SoC architecture, congestion control, Traffic Management, SystemVerilog RTL design, advanced networking architectures, infiniband, collective communication acceleration, 1.6T Ethernet systems, AI HPC interconnects, RDMA packet processing, High-speed SerDes, UCIe, reliability mechanisms, PCIe Gen6, Ultra Ethernet, full ASIC lifecycle, RoCEv2, CXL, Ethernet Scale-Up Networking

Debugging, High-speed digital design, High-bandwidth data movement architectures, Switching fabric design, High-speed interconnects, Memory subsystem design, Low-power methodologies, SoC architecture and integration, Synthesis, Microcontroller-based systems, Performance Analysis, Silicon bring-up, ASIC development flows

Perl, Python, Tcl, FineSim, CTS, POCV concepts, Hspice, primetime, Monte Carlo analysis, STA tools, STA fundamentals, cross-talk, ICC2, Spice simulations, Tempus, Innovus, Signal Integrity, scripting proficiency, Timing Constraints, Parasitic Extraction, noise, ASIC back-end flows, AOCV

rtl development , Verilog, Data movement, Pcie, Computer Architecture, Ethernet, CDC reset architecture, systemverilog, Networking interconnect concepts, UALink, CHI, Microarchitecture development, High-speed interconnects, CCIX, Coherent fabrics, CXL, Hardware design methodology

Pi, PCIe Gen3 4 5 6, ESD Reliability, Memory interface circuits, high-speed Serdes, LPDDRx, DDRx, Si, I O Design fundamentals, GDDRx, Analog Design

Pi, PCIe Gen3 4 5 6, ESD Reliability, Memory interface circuits, high-speed Serdes, LPDDRx, DDRx, Si, GDDRx, Analog Design

Verilog, SVA, formal verification, Assertions, Uvm, debugging complex RTL, systemverilog, Functional verification methodologies, testbench issues, Coverage

C, Debugging, Shell, Verilog, Test Planning, Python, Tcl, Systemc, Power-aware verification, Transaction-level modeling, Assertions, systemverilog, Constrained-random verification, UVM-based testbench development, formal verification, NoC bus and interconnect verification