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RTL Design Lead - PCIe/CXL/UAL/DMA

The Role

AMD-Xilinx is looking for a MTS SoC Architect to join the team in defining the next generation of Adaptive and Embedded SoCs. You will drive novel SoC architecture solutions across a wide range of applications, including Embedded Computing, AI/ML, Data Center, Communications, Automotive, and Aerospace, in close collaboration with customers, partners, product planning, SoC and IP architects, and design & verification teams.

The Person

As a MTS SoC Architect you will help drive new architecture initiatives that leverage the state-of-the-art PCIe, CXL, and Confidential Compute technologies and standards. You will exercise your deep technical expertise and excellent communication skills to collaborate with design and product planning with an eye towards delivering innovative and highly competitive adaptive accelerators and embedded computing solutions.

Key Responsibilities

Hiring with 7+ yrs and responsible for driving the SoC architecture, with a particular focus on I/O subsystems connected over PCIe, UAL or CXL.
Define I/O subsystem and PCIe DMA architectures, including their interactions with internal embedded processor-subsystems, Network on Chip, Memory controllers, and FPGA fabric.
Create flexible and modular I/O subsystem architectures that can be deployed in either chiplet, monolithic or 3D form factors.
Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets.
Define I/O subsystem and DMA hardware, software, and firmware interactions with embedded processing subsystems and external CPUs.
Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase.

Preferred Experience

Strong technical background architecting SoC and I/O subsystems involving PCIe, PCIe-DMA engines, or CXL.
Deep technical knowledge of the PCIe or CXL protocol specifications, and how mandatory and optional protocol features are leveraged in PCIe or CXL devices.
Domain expertise in embedded computing, aerospace & defense, data-center, networking, or automotive industries.
Knowledge of I/O Subsystem and DMA interactions with internal embedded processor-subsystems (x86, RISC-V or ARM) and external host CPUs.
Knowledge of bridging and ordering rule enforcement between on-chip protocols such as AXI, and off-chip protocols such as PCIe desired.
Knowledge of ARM Processors and AXI Interconnects desired.
Knowledge of FPGA and AI/ML Accelerators desired.
Knowledge of boot, security, debug, telemetry and RAS desired.

Academic Credentials

BS/MS/PhD in electrical or computer engineering or related field.

LOCATION: Hyderabad/Bangalore, India

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.

This posting is for an existing vacancy.

PCIE Architect