Ras, DDR, Pcie, Python, Usb, Uefi, BIOS, Perl, System Architecture, Ethernet, protocol analyzers, logic analyzers, CPU subsystems, Oscilloscopes, memory hierarchy, power management, memory technologies, debugging interfaces, SOC design, silicon debug, post-silicon validation, DCI, x86 architecture, Intel Trace Hub

Ras, DDR, Pcie, Python, Usb, Uefi, BIOS, Perl, System Architecture, Ethernet, protocol analyzers, CPU subsystems, logic analyzers, Oscilloscopes, memory hierarchy, power management, memory technologies, debugging interfaces, SOC design, silicon debug, post-silicon validation, DCI, x86 architecture, Intel Trace Hub

C, Soc Architecture, Automation, Python, Multi-core CPU systems, Memory subsystem coherency, Post-silicon validation, Interconnects, CPU microarchitecture, Memory subsystems, Debug or silicon bring-up, Pipeline cache, Exception debug flows, ARM architecture fundamentals, Assembly

logic bist , Unix, Linux, Perl, Python, Tcl, DFT verification, Memory BIST, Cadence DFT solutions, Design-for-Test architecture, Fault Simulation, JTAG IEEE 1149.1, DFT methodologies, Siemens Tessent, At-speed testing, Scan compression, Scan architecture, ATPG, IJTAG IEEE 1687