Java, Core Java, Spring Boot, API design, Scalability, Automation, Performance, Microservices, DevOps practices, Reliability

FineSim, Synopsys VCS, SerDes verification, analog mixed signal verification, Xcelium, Verilog-AMS, high-speed design, Cadence Virtuoso, Uvm, SystemVerilog-RNM, Spectre

clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis

Verplex LEC, spyglass, Verilog RTL coding, high-performance memory subsystems, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, ASIC debugging

high-performance datapath architecture, ASIC SoC architecture, congestion control, Traffic Management, SystemVerilog RTL design, advanced networking architectures, infiniband, collective communication acceleration, 1.6T Ethernet systems, AI HPC interconnects, RDMA packet processing, High-speed SerDes, UCIe, reliability mechanisms, PCIe Gen6, Ultra Ethernet, full ASIC lifecycle, RoCEv2, CXL, Ethernet Scale-Up Networking

scoreboard , Nvme, Pcie, Verilog, System Verilog, DDR, Assertions, Functional coverage coding, RTL debugging, Code Coverage analysis, Axi, AMBA protocols, Uvm, AHB

Distributed systems data architecture and performance optimization, AI technologies

rtl development , Debugging, Soc Architecture, Pcie, Systemc, UCIe, CHI protocols, Microarchitecture understanding, AMBA, Axi, Memory subsystem architecture, CXL, Performance Analysis, Silicon bring-up

system-on-chip (SoC) architecture, MATLAB, Xml, Python, subsystem integration methodologies, Cortex-M families and their ecosystem, digital design principles, hardware software interface design, estimation tools, architecture trade-off analysis, Simulators, Embedded System Design, sims, design-oriented tools, waveforms, ARM Cortex processor architectures, Spreadsheets