Scripting, Clp, Automation, LINT, cdc, Prelayout STA, SDC generation, SDC development, LEC, Low power aspects, RTL Netlist based static checks, Timing Closure, Synthesis, Postlayout STA, Timing Constraints

Clp, Automation, SDC constraints development, Synthesis, Timing Closure, LINT, LEC, AI scripting, Prelayout STA, cdc, Postlayout STA, RTL Netlist based static checks, SDC generation

Clp, automation, Scripting, LINT, cdc, SDC generation, SDC development, LEC, RTL Netlist based static checks, prelayout STA, low power aspects, postlayout STA, Synthesis, demotion, Dft, Timing Constraints, Timing Closure, Verification, promotion, equivalence checking

synopsys primetime , Perl scripting, Static Timing Analysis, SDC constraints, RTL Synthesis, STA timing constraints, mmc, Timing optimization, Critical path analysis, ASIC SoC implementation and signoff methodologies, Setup hold analysis, Timing Closure, MCMM, Synopsys Design Compiler, ECOs and timing fixes