bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

pdk development , Python, Skill, LVS, Cadence Virtuoso, DRC, PEX

routing, VCAR auto routing, Cadence Design Suite, Assura Calibre PVS, QRC extraction, IC617 Virtuoso tools, constraints-driven layout, BCD technology, Modgens, Clones, schematic driven layout design, Analog IC layout and verification tools