cadence spectre , Python, Analog Mixed Signal Verification, Skill, Xcelium, SystemVerilog-RNM, Uvm, Model vs Schematic Comparison, High-speed Design AMS Verification, Behavioral Modelling, Synopsys VCS FineSim, Verilog-AMS, AMS Designer, Synopsys AMS tools, Cadence Virtuoso, Mixed Signal Modelling, SerDes Verification

regulatory documentation, test lab processes, Risk Assessment, EMCD, LVD directives of CE, validation requirements, Rohs, UKCA, Product Compliance Testing, DoC, compliance standards CE, board-level compliance and certification flow

Siem Tools, Ips, Firewalls, Vulnerability Assessments, Ids, Security Documentation, risk assessments, threat visibility, patch compliance, endpoint protection systems, incident response playbooks, audits, compliance checks

Uart, Nvme, Verilog, I2c, Pcie, Flash, system debug infrastructure, Uvm, system memory hierarchy, AMBA bus protocols, systemverilog, digital ASIC design and verification, formal verification, ARM cores and related infrastructure, CXL, DRAM, CPUSS C-based verification, multi-core SOC, SSP

Iso 14971, Iso 13485, DHF documentation, FDA 21 CFR Part 820, quality engineering, Microsoft Office Applications

export-import documentation, Customs Clearance, GST refund, EXIM reporting, high sea sales, DGFT/ICEGATE knowledge

Bug Fixing, Ethernet, requirement engineering, Design Verification, brake systems, software test specifications, WTB, V-model approach, EN 50657, IEC 50128, traction control, software upgrades, setpoint generation, IEC 61131, IEC 61375, SWrS interface specifications, Communication Protocols, code reviews, TRDP, interface specifications, functional block diagrams, RArS, control logic development, MVB, logic block diagrams