Verilog, Sata, Python, Perl, Usb, Uvm, PCI Express, VMM, systemverilog

C, Debugging, Soc Architecture, Perl, Verilog, Python, CPU architecture, AMBA protocols, systemverilog, Emulation, Simulation, Verification fundamentals, Assembly

Makefile, Windows, Pcie, Perl, Linux, Verilog, System Verilog, IP level ASIC verification, LLMs, AI Agents, HLS tools, UVM testbenches, DMA verification, Simulation profile efficiency improvement, UVM based verification frameworks, CXL

Usb, Perl, Verilog, Sata, Python, Testbench development using SystemVerilog, DV methodologies, PCI Express, Uvm, verification tools for simulation and debug, systemverilog, functional coverage based constrained random verification, VMM

Windows, Pcie, Linux, Verilog, System Verilog, automation, HLS tools, DMA verification, CXL, simulation profile efficiency improvement, Ai, Uvm

C, Opengl, Opencl, D3D, Uvm, systemverilog