boundary scan , logic bist , DFT techniques, Memory BIST, IDDQ, Bridging fault generation, Pin-muxing, At-speed Path delay, SDD, At-speed Scan Test-clocking, Scan On-Chip Compression, Test vector Stuck-at, Analog Testing, on-chip compression, high test coverage, timing SDF, Scan Insertion, Test Modes implementation and verification, simulations at gate level

Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan