Verilog, Python Scripting, Spice, AI-assisted tools, Logic schematic analysis, gate level simulations, Timing Analysis

Uart, Verilog, Embedded Software, Spi, C, Synplicity, Silicon Validation, SERDES architecture, high-speed serial communications protocols, JESD204C, JESD204B, PMA features, Synthesis Placement constraints, I3C, protocol exercisers, Oscilloscopes, HDMI, STA constraint definition, Timing Closure, Failure Analysis, Board level debug, Modelsim, DisplayPort, VHDL, integrated logic analyzers, USB3.2, digital analyzers, AMBA protocols, Debug

Selenium, Jira, Azure DevOps

Technical Leadership, JIRA, Agile Methodologies, mbse, Enterprise Architect, Ethernet, Cybersecurity, Doors, Lin, Can, SysML, requirements system architecture integration and validation, Body Control systems, vehicle E E architectures and networks, Uds, Supplier Management, Canoe, DoIP, Canalyzer, vehicle electronics systems, Polarion, Diagnostics, Software Defined Vehicle architectures

snowflake , containerization , Java, Sql, Azure Functions, Talend, Kubernetes, Docker, Microsoft Azure, Spring-based frameworks, Git-based source control, Pentaho Kettle, Microservices architectures, Event-driven systems, Automated testing frameworks, Serverless technologies, CI/CD pipelines

power optimization , Verilog, Spi, C, Uart, C++, Ethernet Switching, Tcl, Python, Synthesis, Simulation, FPGA emulation, Timing Closure, Pre-silicon system validation, Area optimization, Microcontroller-based subsystems, systemverilog, Digital design methodologies, I²C, Packet processing, Timing Analysis, TSN