clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis

Microprocessor and common SoC hardware blocks, Display Graphics, Interconnects, Commercialization of System-level power features, Electrical Engineering, Application processor, Modem Communication systems design, Power use case modeling tools and methodologies

Ethernet, high-performance datapath architecture, RDMA, scalable fabric architectures, high-speed connectivity silicon, ASIC SoC architecture, congestion control, Traffic Management, SystemVerilog RTL design

Golang, Distributed Systems, Containers, Technical Leadership, Automation, File Systems, Microservices, Cloud Storage, Infrastructure Services, Databases, Gcp, Scalability, Rest Apis, Azure, Python, Kubernetes, AWS, Software Systems Engineering, Go, Security, Reliability, Observability

Spi, Uart, Soc, Pwm, MATLAB, Rtos, Bsp, I2c, Ethernet, Doors, Can, Simulink, Fmea, IEC 60601, IEC 62304, ADC, MCU, Iso 14971, Embedded Coder, hal

Die file generation, Feed-through planning, PnR implementation, SoC Full-chip floorplanning, PG creation and push-down methodologies, Hierarchical design implementation, Scripting flow deployment for SoC Blocks, Physical Verification, SoC RTL to GDSII implementation, RDL knowledge, Sta

C, Python, LabVIEW, SoC System-on-Chip, precision measurement techniques, voltage regulators, reference circuits, bench characterization of Analog Digital and Mixed-Signal IPs, Microcontrollers