Shell, Perl, Python, Uvm, VHDL Design, systemverilog

DDR, System Verilog, test plan generation, environment development, Design Verification, Uvm, GDDR, memory IP, environment planning, Functional Verification, IP verification, HBM

Scripts, Test Plans, System Verilog, Sequencers, Scoreboards, Debug, Uvm

Verilog, Python, Tcl, Fusion Compiler, LP signoff tools, clock gating, LEC, UPF, Synthesis tools, VHDL, QoR optimization, Genus, Equivalence Checking

Software Development Lifecycle (SDLC), Verilog, FPGA Prototyping, AI tools, Profiling, Emulation, Performance characterization, Benchmarking, Root-cause analysis, systemverilog

Unix, C, Linux, Verilog, Tcl, VHDL, Spice

Soc, Verilog, Subsystem Verification, Functional Assertion Coverage, Ip, Uvm, UPF, ARM Cores, RTL Debug, systemverilog, AMBA, Axi, VHDL, formal verification, Low Power, CPF, AHB

Tcl Scripting, FPGA Design, RTL design using Verilog