Perl, Python, Tcl, automation, Synthesis, FPGA prototyping, multi-FPGA partitioning, ZeBu, Veloce, Timing Closure, bitfile generation, FPGA debug, Emulation, HW SW debug, FPGA board bring-up, RTL analysis

model design , Eda, Programming Languages, Technical Documentation, Integration, architecture and design tools, Synthesis, Place And Route, circuit specifications, layout flow, logic designs, scripting tools, ASIC Design, custom circuit design, Verification, design verification methods, RTL to GDS Flow, virtuoso, system simulations, Validation, IP block SoC development