Coding Methodology, RTL Linting, Synthesis, Design Compiler, primetime, Timing Closure, Genus, SDC Constraints, Tempus, systemverilog

Design Compiler, primetime, Vivado, SDC timing constraints, Genus, Tempus, VLIW, FPGA prototyping, systemverilog

Synthesis, multi-clock designs, formal verification, ECO fixes, SoC clocking reset architecture, Verilog System-Verilog, Logic design RTL coding, SoC design and integration, asynchronous interfaces