System Verilog, Assertions SVA, AMBA protocols AXI AHB APB, ARM Cortex-M33, Peripheral interfaces SPI UART I2C I2S TDM, AMS co-sim, RISC-V SoCs, Uvm, Functional coverage, Mixed-signal verification environments, Low-power verification UPF CPF

Ovm, Database Management, Verilog, System Verilog, silicon debug, verification management tools, formal property checking tools, Uvm, memory controller protocols, assertion and metric-driven verification, Synopsys VCS, gate level simulation, power verification, Cadence IES, reset verification, Cadence Jasper, contention checking, calibration board skew and jitter modeling

Perl, Shell scripting, Python, Tcl, PERC, Calibre DRC, ERC, LVS, physical signoff methodologies

Perl, Shell scripting, Python, Tcl, PERC, Calibre DRC, ERC, LVS, physical signoff methodologies

arm architecture , Branch-Predictor Frontend Load-Store verification, cache coherency concepts, stimulus generation using RIS tools, ARM v9 architecture, CPU microarchitecture verification

model checking, Logical Equivalence Checking, formal verification, Advanced Computer Architecture, Micro-architecture Concepts, PSL, SVA, systemverilog

AI ML techniques, Uvm, systemverilog, Coverage-driven verification

Usb, Ethernet, Vcs, Pcie, DDR, AHB, LPDDR, debug using industry-standard simulators, FPGA prototyping, systemverilog, Ace, constrained random methodology, Xcelium, SVA, CPF, CXL, APB, Axi, Questa, Uvm, UPF, Emulation, coverage-driven verification, CHI, AMBA, low-power verification, IP and SoC level verification, VIP integration and customization, high-speed protocols

Verification methodologies such as UVM, Understanding of StarRC Calibre parasitic extraction flow, NAND Flash memory design, Test Bench development in System Verilog

Unix, Usb, Linux, System Verilog, Jtag, Ethernet, Python, Perl, Pcie, TSN, UVM methodology, Design for Debug, ARM based SoC verification