transistor-level design and simulation, PEX, post-layout verification, LVS, noise analysis, Analog Circuit Design, Spectre, advanced CMOS technology nodes, DRC, layout sensitivity, linearity matching, mixed-signal IC design, Cadence Virtuoso

Matlab, Worst case identification, Process technologies tradeoffs, Monte Carlo analysis, Simulation verification, Block level topology selection, IC system partitioning, Physical layout management, AMs, Simulation on modern CAD tools, Analog Circuit Design, Architectural tradeoff analysis, Schematic generation, Spectre, Cadence tool set, Top level simulation, Simplis, Post layout parasitic extraction

FineSim, SPICE-based simulators, Analog circuit design fundamentals, IO Circuit Design, IO architectures and standards, LVS, CMOS device physics, reliability checks, Spectre, EMIR, Hspice, ESD design methodologies, DRC, Cadence Virtuoso

C, Perl, Python, Tcl, mixed-signal circuit design, SPICE simulation, IC layout, verilog a, Analog Circuit Design

Dll, Dac, ADC, FinFET process technologies, Voltage detectors, Oscillators, Deep sub-micron technologies, Mixed Signal Design, Mixed-mode simulations, Voltage and current references, Pll, Simulation of analog blocks, power management, Clock management, Statistical simulations, Switching regulators, Signal Processing

multilayer PCB layout, mixed-signal HW design, analog measurement, Power Distribution, Power Electronics, EMI EMC design considerations

bandgap references , Current Mirrors, Transistor level architectures, Simulation and verification, Schmitt Trigger, ESD protection circuits for CMOS IC, Transistor layout fabrication process, Amplifiers, Analog Circuit Design, Level Shifter, Schematic generation, High voltage design rules, LDMOS, Comparators, Power FET technology, MOS Diodes, Mismatch and Monte Carlo analysis

bandgap references , PLLs, mixed-signal architectures, post-layout verification, DC-DC converters, BCD processes, Bias Circuits, Comparators, SAR ADCs, corner analysis, LDOs, noise mismatch stability analysis, Voltage References, parasitic effects, matching common-centroid structures, Oscillators, feedback systems, layout concepts, Spectre, Monte Carlo simulations, Analog Mixed-Signal IC Design, Buck regulators, analog floorplanning, Cadence Virtuoso, low-power design techniques

DFE, Duty Cycle Correction, BGR, Oscillators, High-speed clock distribution, Rx CDR, Tx Serializer Output Driver, CTLE, Generic Analog Circuits, Analog Circuit Design, EDA Tools, Bias Circuits, Deserializer, Circuit design simulation and analysis, LDO, Lower Nodes Experience, Amplifiers, VGA, Comparators, Power Management Circuits, High-Speed SerDes Tx and Rx blocks