Synthesis, Scripting automation, EDA Tools, Mixed signal complex IPs, AI and AI-enabled workflows

boundary scan , Jtag, Perl, Python, Tcl, LINT, ASIC design flow, DFT DRC, cdc, Analog DFT, MBIST, Scan compression, Scan stitching, Dft, Low power DFT Techniques, ATPG, Low Power Checks, RTL Coding, ATPG Coverage improvement, LBIST, DFT STA Constraint development, Siemen’s DFT EDA tools

Rhel, Shell Scripting, linux, IBM Power Systems, IBM PowerVC

C, Scripting Languages, Python, Sql, HTML

test automation, Embedded Programming, Soc Architecture, ARM cores, validation frameworks, AI frameworks for SoC Validation

Cadence - Virtuoso, Perl, Python, Tcl, Spice Simulator, Unix environment and shell scripting, SV and UVM testbench development, Verilog-AMS, Verilog Hdl, Verilog-D, Verilog-A

Scripting Languages, Sql, C, Python, HTML