code coverage , System Verilog, IC verification tools, Cover groups, DIMM, DDR5, DDR4, Uvm, Functional coverage, Assertions, LPDDR5

UFS (Universal Flash Storage), C, C++, Vcs, Makefile, Perl, Verilog, Ethernet, System Verilog, System Verilog verification language, Uvm, Synopsys VIPs, Asic Design Verification, ASIC flow, AXI-AMBA protocol variants, PCIe Protocol, waveform analyzer

pdk development , Python, PEX, Skill, DRC, LVS, Cadence Virtuoso

Autocad, Catia V5, Wiring harness design, regular expressions, ATIM, VeSyS2.0 wiring harness design tool, Wiring harness testing and inspection, Basic Python scripting, IPC-620 standard, CAD Tools, MENTOR TOOLS

Debugging, Soc Architecture, Perl, Verilog, Python, Tcl, Sta, High-speed digital design, cdc, Low-power design concepts, IP integration, systemverilog, FPGA prototyping, Rtl Design, Synthesis, Micro-architecture