Ecos, Python, Perl, Tcl, Sta, CTS, Antenna, Cadence Innovus, LVS, routing optimization, congestion optimization, routing issues, SDC, MMMC, advanced technology nodes, full-chip physical implementation, constraint development, floorplanning, PPA improvements, EM, Ir, Timing Analysis, signoff, setup hold closure, SI crosstalk, DRC, Timing Closure, complex SoC designs, Placement

Scripting, RTL-to-GDSII Execution, SoC-Level Physical Design, Cross-Functional Collaboration, Timing PPA Closure, Architecture Methodology, SerDes IP Integration, Team Leadership Mentorship, Technical Ownership Project Planning, Stakeholder Vendor Alignment, Advanced Technology Nodes, Risk Issue Management, EDA Tool Proficiency

power integrity , Routing, CTS, primetime, Fusion Compiler, floorplanning, ICC2, PDN Placement, Physical Verification, Calibre, Innovus, SoC ASIC Physical Design, Timing Closure, signoff methodologies

EM IR understanding and fixes, PnR-Floorplan Macro placement, STA analysis, Util area reduction experiments, ECO cycle, Physical aware Synthesis using FC, PV closure, Density Congestion Timing issues and fixes