Tcl Scripting, Shell scripting, Python, Routing, Perl, Sta, Signoff, CTS, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, LVS, Signal Integrity, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2

congestion management , Python, Routing, Perl, Tcl, Sta, CTS, Advanced Floorplanning, Cadence Innovus, Physical Signoff, LVS, Fusion Compiler FC, UPF, MMMC, Power Distribution Network, Antenna, Multi-voltage design implementation, Placement Optimization, EM, Physical Verification, Ir, low power design, Physical Design, Timing Closure, ECO Implementation, DRC

Scripting, RTL-to-GDSII Execution, SoC-Level Physical Design, Cross-Functional Collaboration, Timing PPA Closure, Architecture Methodology, SerDes IP Integration, Team Leadership Mentorship, Technical Ownership Project Planning, Stakeholder Vendor Alignment, Advanced Technology Nodes, Risk Issue Management, EDA Tool Proficiency

power integrity , Routing, CTS, primetime, Fusion Compiler, floorplanning, ICC2, PDN Placement, Physical Verification, Calibre, Innovus, SoC ASIC Physical Design, Timing Closure, signoff methodologies

EM IR understanding and fixes, PnR-Floorplan Macro placement, STA analysis, Util area reduction experiments, ECO cycle, Physical aware Synthesis using FC, PV closure, Density Congestion Timing issues and fixes