microprocessor design-for-debug (DFD) logic, C, C++, test-planning and execution, coverage planning, power management verification, SystemVerilog testbench development, coverage closure, Asic Design Verification, Cache coherency and data-consistency verification, low power verification flows, functional coverage

microprocessor design-for-debug (DFD) logic, C, C++, coverage closure, coverage planning, power management verification, low power verification flows, Asic Design Verification, test-planning and execution, Cache coherency and data-consistency verification, SystemVerilog testbench development, functional coverage

Verilog, systemverilog, Digital and analog simulation tools, Uvm, PrimeSim, Verification strategy, Design Verification, Hspice, FineSim