Formal verification (LEC), Static Timing Analysis (STA), Hierarchical synthesis flows, power analysis, SystemVerilog RTL, Logic Synthesis, Physical-Aware Synthesis, Signal integrity analysis, PPA optimization, Floorplan-driven synthesis, UPF management

synopsys primetime , Physical Design flow, advanced technology nodes, Timing Closure, clocking architecture, CDC concepts

synopsys primetime , Ecos, Python Scripting, Sta, Physical Design concepts, SDC, SI analysis, MCMM, MMMC, SOCV, Timing Closure, AOCV, Innovus, Fusion Compiler, StarRC, ICC2, Tempus

synopsys primetime , Perl, Python, Tcl, timing optimization techniques, MMMC analysis