rtl development , Vcs, Gdb, Verilog, ASIC design flow, floor-planning, Timing Analysis, Logic Synthesis, Eco, design and verification tools, micro-architecture, Debussy, bring-up lab debug

Verilog Hdl, LINT, cdc, Hands-on RTL development expertise, Clock power domain implementations, Synthesis timing analysis, digital hardware design, Static checks, Power checks, RDC, Writing design micro-architecture specifications, Power management and low-power design techniques, Design for IPs

rtl development , static timing analysis, Verilog, Digital Signal Processing, LINT, Synthesis, Debug, LEC, Simulation, Matlab modeling, FPGA prototyping

static timing analysis, Perl, Python, LINT, EDA tools for synthesis, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques

Static Timing Analysis (STA), Fpga, Synthesis, ASIC design flows and methodology, low power design implementation, power gating, sign-off optimizations, multi-voltage domains, deep sub-micron technology, Physical Design, IP integration, DSP systems, sign-off convergence, SOC place and route, Circuit Design, device physics

Spectrum Analyzer, Signal Integrity and Power Integrity Analysis, Oscilloscope, Logic Analyzer, Analog and Digital Circuit Design, Network Analyzer, PCB Design and Layout Review, Signal Conditioning Circuits, Communication Protocols SPI I2C UART CAN RS-485 Ethernet, Hardware Debugging and Failure Analysis, Microcontrollers DSPs and FPGA Integration, LTspice PSpice, Power Supply Design, EMI EMC Design and Debugging, Mixed Signal Design Architecture, ADC DAC Interface Design

redhawk , Shell, PERL, Verilog, Tcl, place and route methodologies, low power physical design flows and methodologies, Fusion Compiler, physical implementation and analysis tools, timing and signal integrity analysis, Innovus, Calibre, VHDL, power integrity and reliability analysis, power grid planning and implementation, Starrcxt, timing optimization and timing closure, placement and optimization, metal-only ECO implementation, floorplan exploration and optimization, Clock Tree Synthesis