simulator , compiler , C, Verilog, Arm, Python, System Verilog, Embedded C Verification, Assembler, Floating point instructions implementation verification, RISC-V, Uvm, Logic Verification, processor toolchains, functional processor simulators

Perl scripting, Verilog, C, Python, Uvm, AHB, systemverilog, Axi

UFS (Universal Flash Storage), C, C++, Makefile, Perl, Verilog, Ethernet, System Verilog, Verification tools such as VCS, System Verilog verification language, Uvm, Synopsys VIPs, Waveform analyzer, Asic Design Verification, ASIC flow, AXI-AMBA protocol variants, PCIe Protocol

Arm, Python, RTL simulation, Debug, functional coverage closure, RISC-V, regression automation, x86 architecture, Uvm, SVA, systemverilog

Bus protocols - APB, C, Usb, Uart, Spi, Test Plan Creation, Pcie, I2c, System Verilog, Bus interconnects, Checkers, i2s, Uvm, Functional coverage, DP, Sd, AHB, Verification methodology, Gate-level simulations, Scoreboards, Gate Level Power-Aware simulations, Axi

OASIS, Python, Shell, Perl, Tcl, PERC, LVS, CDL, Dfm, SVRF-based automation, Verilog netlists, XOR methodologies, layout connectivity, antenna density, ASIC physical verification, Spice, Cadence Pegasus, DEF, LEF, Siemens Calibre nmDRC, metal-fill, ERC, DRC, Synopsys ICV, GDSII