rtl development , static timing analysis, Verilog, Digital Signal Processing, LINT, Synthesis, Debug, LEC, Simulation, Matlab modeling, FPGA prototyping

Spi, Embedded Controllers, Verilog, I2c, Uart, Can, cdc, testability requirements, Simulation, Dft, Synthesis, linting, Motor Control Systems, RTL Coding, GPIO Timers, debug activities, PWM Modules, Scan Insertion, DMA Interrupt Controllers, Ethernet Interfaces, systemverilog, Quality Checks, Functional Verification, Physical Design, Industrial Communication Interfaces

Automation scripts, formal verification, Gate Level Netlist, Power Estimation, RTL Lint, RTL DFT Analysis, Logic Physical Synthesis

Verilog, Python, bus architectures, Synopsys, performance modeling tools, Cadence Tools, accelerators, memory hierarchies, low-power design techniques, arithmetic units

Verilog, Logic Design, Physical Design, Timing Constraints, RTL constraints, LINT, Vlsi, timing exceptions, System-Verilog, cdc

rtl development , Jtag, Verilog, I2c, ASIC design flow, Timing Analysis, System-Verilog, mixed-signal chips, SPMI, Custom Digital Design, Behavioral Circuit Modeling, Dft, power management solutions