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Showing 3 jobs
Skills:
UVM methodology, System Verilog coding, UVM-based verification frameworks
Skills:
Perl, Python, Tcl, Xcelium simulation, vManager, Real-Number Modeling, Verilog-AMS, JasperGold, Uvm, SVA, systemverilog
Skills:
Bus protocols - APB, C, Usb, Uart, Spi, Test Plan Creation, Pcie, I2c, System Verilog, Bus interconnects, Checkers, i2s, Uvm, Functional coverage, DP, Sd, AHB, Verification methodology, Gate-level simulations, Scoreboards, Gate Level Power-Aware simulations, Axi
