power optimization , routing, CTS, ECO execution, floorplanning, Cadence, Mentor, LVS, Signal Integrity, EDA Tools, Timing Closure, DRC, Placement, Synopsys

Solidworks, Autocad, Autodesk Inventor

Tcl Scripting, System Verilog, Synopsys Mentor VIPs, verification methodologies, performance power optimization, random constraint-based testing, PCIe Gen3 Gen4 Gen5 Gen6, SMMU, Coresight architecture, Uvm, assertion-based verification, CHI protocols, UPF, Axi, formal verification, CXL 1.1 2.0 3.0, power-aware verification, coverage-driven testing, SVA

Vcs, programming, Scripting, Python, System Verilog, Asic verification, NCSim, verification of HBM memory interfaces, UVM testbench development, verification of SerDes IP block interfaces, Modelsim, formal model equivalence checking

product life cycle , SAE AS50881, VESYS 2020.1, basic python scripting, ATIM, Excel automation, CAD Tools, Catia V5, MS-VISIO 2016, IPC-610, WHMA-620, Product configuration, regular expressions, AutoCAD premium, MENTOR TOOLS, MIL-Standards for wiring harness

code coverage , System Verilog, IC verification tools, Cover groups, DIMM, DDR5, DDR4, Uvm, Functional coverage, Assertions, LPDDR5