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SENIOR STA SILICON DESIGN ENGINEER

Key Responsibilities

Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA
Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)
Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip.
Ensuring Subsystem/full chip level Interface timing closure along DRV closure
Generating timing ECO using tools DMSA/Tweaker.

Preferred Experience

4-5 years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.
Experience with analyzing the timing reports and identifying both the design and constraints related issues.
Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc.
Experience in timing closure of high frequency blocks & subsystems (> Ghz range )
Good Understanding of DFT modes requirements for timing signoff
Good understanding of SDC constraints, OCV,AOCV,POCV analysis.
Strong TCL/scripting knowledge is mandatory.

 

ACADEMIC CREDENTIALS: 

Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.

This posting is for an existing vacancy.

Senior STA Design Engineer