Data Mining, Threat Intelligence, Rule Signature Development, Programming Scripting, Vulnerability Exploit Research, Security Frameworks, Identity Security Expertise, Adversary Tradecraft, AI ML in Threat Research, Attack Vectors

UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

Technical Leadership, Soc, ASIC implementation, custom IP integration, physical design flows, custom silicon design, hardware-software co-design, mass production, system-level debug, silicon bring-up, SoC development programs, hardware-software co-design principles, root-cause analysis

clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis

power integrity , Static Timing Analysis (STA), Python Scripting, MCMM analysis, floorplanning, Netlist to signoff GDSII, CTS routing, Cadence Innovus, Physical design signoff, ECO implementation, Timing Closure, Timing constraints setup hold closure, Placement, Full-chip physical design flow

Perl, Python, Tcl, Power integrity analysis, Cadence Voltus, Ansys RedHawk, Static and dynamic IR analysis, Power grid optimization

Perl, Python, Tcl, RTL-to-GDSII design flow, EDA Tools, CAD methodologies

Die file generation, Feed-through planning, PnR implementation, SoC Full-chip floorplanning, PG creation and push-down methodologies, Hierarchical design implementation, Scripting flow deployment for SoC Blocks, Physical Verification, SoC RTL to GDSII implementation, RDL knowledge, Sta

Python Scripting, Power Bi, Qgis, Advanced Excel, InfoWorks WS Pro, Synergi, ArcGIS Pro