test mode timing constraints definition, DFT concepts, Scan Insertion, Transition delay test coverage analysis, equivalence check DFT DRC rules, Synopsis TetraMax, simulating test vectors, ATPG coverage analysis, Cadence Encounter Test, DFTMax, ASIC DFT, timing fixes

boundary scan , Jtag, Perl, Tcl, Scan Insertion, Yield analysis, MBIST, Debugging silicon test issues, ATPG, Repair logic at RTL gate level, Debug test pattern issues, Test pattern validation, Test pattern development