power optimization , Perl Scripting, Tcl, CTS, Block level PnR convergence, advanced STA concepts, Cadence Innovus, LVS, timing convergence of high frequency data-path intensive Cores, Physical Verification, timing convergence in PTSI Tempus, Timing Closure, DRC, PDN, Physical Design Implementation, PD implementation of PPA critical Cores, Floor-planning, Place And Route, Synopsys ICC2, clocking architecture, formal verification

Routing, IR Drop Analysis, Synthesis, ICC Innovus, Extraction, floorplanning, Placement, P R skills, Signal Integrity, Power Physical Verification, GDSII