Java, Api Management, Devops, Cloud Architecture, Azure Functions, Compliance, Azure Cloud Integrations, Logic Apps, Vendor Management, Security, Integration platforms, Service Bus, Event Grid, Azure Monitor

Technical Leadership, Soc, ASIC implementation, custom IP integration, physical design flows, custom silicon design, hardware-software co-design, mass production, system-level debug, silicon bring-up, SoC development programs, hardware-software co-design principles, root-cause analysis

clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis

power integrity , Static Timing Analysis (STA), Python Scripting, MCMM analysis, floorplanning, Netlist to signoff GDSII, CTS routing, Cadence Innovus, Physical design signoff, ECO implementation, Timing Closure, Timing constraints setup hold closure, Placement, Full-chip physical design flow

Software Development, Apache Flink, Apache Kafka, Apache Druid, OpenSearch, distributed systems design

SystemVerilog Assertions (SVA), C, C++, UNIX, MATLAB, Continuous Integration, Perl, Verilog, Shell scripting, Python, Tcl, AI/ML based computer vision algorithms, API Architecture Design, Uvm, AMBA interfaces, systemverilog, VHDL, Project Management, Image processing algorithms, DDR specifications, ASIC RTL design

Ethernet, high-performance datapath architecture, RDMA, scalable fabric architectures, high-speed connectivity silicon, ASIC SoC architecture, congestion control, Traffic Management, SystemVerilog RTL design

System Testing, Robot Framework, Ipv4, Spirent, L2vpn, L3vpn, Ipv6, Ixia, VLAN, BGP, Qos, Ldp, Rsvp, OSPF, Python, Networking Systems Engineering, Solution Validation, IS-IS, Junos EVO, Mpls

Java, Ml, C, Scala, Cloud Infrastructure, Python, Go, Ai, Observability, Tooling