conformal lec , Clp, Perl, Python, Tcl, Fusion Compiler, Formality, LEC, MCMM methodologies, UPF, Cadence Genus, Synthesis, Synopsys Design Compiler, RTL-to-GDS, CPF, Low Power Verification

synopsys primetime , Static Timing Analysis, Perl, Python, Tcl, SDC constraints, RTL Synthesis, STA timing constraints, ASIC SoC implementation and signoff methodologies, Synopsys Design Compiler, ECOs and timing fixes, critical path analysis, implementation flows, RTL-to-gate synthesis, Fusion Compiler, setup hold analysis, Timing Closure, timing optimization

Static timing analysis, design optimization, SDC constraints, Logic Synthesis, Timing ECOs, Clock-gating checks, CDC-related timing issues, UPF, ECO implementation, MMMC timing analysis, Timing Closure, Formal equivalence checking, CPF, Low-power design methodologies, PPA optimization, Physical-aware RTL-to-gate synthesis

Verilog, System Verilog, python, Perl, Sta, Synthesis, Physical Verification, CTS, DFT tools, Extraction, Timing Analysis, Place And Route, Cadence, Synopsys

telemetry , Automation, Synchronization, Data Replication, Replication, Scalability, Rate-limiting, Redundancy, Automatic failover, Throttling, System Design Architecture, formal verification, Load-shedding

UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis

production readiness , power analysis, Design Reviews, Silicon Bring-up, PnR Implementation, Verification, Physical Design, Placement, Floor Planning, ASIC Design, Low Power Verification, Rtl Design