Verilog, debug tools like Debussy GDB, bring-up lab debug, ASIC design flow, floor-planning, Timing Analysis, VCS or equivalent simulation tools, Eco, Rtl Design

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation