Vcs, Verilog, System Verilog, System Testing, LINT, cdc, Flow automation, Timing-analysis, System Validation, Gate-level understanding of RTL and Synthesis, Rtl Design, SW HW bring-up, spyglass, Implementation specification, ASIC Design, Power-optimization, System debug, formal verification, Timing Analysis

Vcs, System Verilog, ATE patterns, JTAG protocols, Logic Equivalency checking, ATPG, Post-silicon validation, Scan and BIST architectures, Gate level simulation debugging