Similar Jobs - 68177957

Showing 5 jobs

ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years

Cisco Live

10-12 yrs

Bengaluru, India

Skills:

System Verilog, Gate Level Simulations, Building test benches, ASIC verification using UVM, formal verification

Early Applicant

ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years

Cisco Home

10-12 yrs

Bengaluru, India

Skills:

Perl, Python, System Verilog, Test benches, Zebu, Veloce, ASIC verification using UVM, Palladium, HAPS

Early Applicant

Staff Engineer, VLSI Design Engineering (UVM, System Verilog) with 8 to 12 years of experience

Sandisk

8-12 yrs

Bengaluru, India

Skills:

UVM (Universal Verification Methodology), System Verilog Assertions (SVA), C, Verilog, Debugging, systemverilog, Regression management, Assertion-based verification, JasperGold Formal, Xcelium simulator, Verdi Debugger, Checkers, Verification automation tools and scripts, Bus functional models, Functional coverage-driven verification, NAND flash memory protocols, Scoreboards, Memory design verification, Monitors, Formal verification tools

Early Applicant

DFT DV Engineer | 7+ years | DFT/DV/UVM/System Verilog

CISCO Credit

8-10 yrs

Bengaluru, India

Skills:

boundary scan , Perl, System Verilog, Python, Tcl, scan architecture, MBIST, DVE Verdi, JTAG protocol, Uvm

Early Applicant

DFT DV Engineer | 7+ years | DFT/DV/UVM/System Verilog

Cisco DevNet

8-10 yrs

Bengaluru, India

Skills:

boundary scan , Perl, Python, System Verilog, Tcl, Test Planning, scan architecture, MBIST, JTAG protocol, Uvm, DFT verification, Verdi, DVE, testbench development

Early Applicant