Python, Tcl, Perl, yield optimization, full-chip timing closure, Calibre, floorplanning, routing optimization, design-for-manufacturability, power-aware sign-off, end-to-end tapeout ownership, primetime, CPF, power grid design, SI crosstalk derates, IR EM sign-off, UPF, AOCV, ESD compliance, ASIC SoC physical design, bump planning, Cadence Innovus, OCV, CTS, DFT integration, CRPR, Voltus, POCV, STA concepts