Route, Rtl Design, Timing Closure, SDC coding and debug, Synthesis, Physical Verification, AMD block TileBuilder, Low power physical design implementation flows, Place And Route

Makefile, Perl, Route, Scripting, Python, Tcl, Sta, CTS, debug skills, Mentor, Cadence, Physical Design, Physical Verification, EMIR, PNR, ML techniques, SDC coding, Timing Closure, Synopsys